With prescale = 1 you can easily get a race-condition, let's say int0 triggers while tcnt1 is at 65500. Saving the processor-registers costs 60 cycles, the additional calculations till you read it, say 300.
In the very moment you read tcnt1, it is already overflown and shows a value of 364.
As the overflow-ISR is blocked while the int0-ISR is executed, the overflow is not taken care of. This happens only later, after the int0-ISR is left, but then the overflow doesn't make it into the calculation and random values are shown.
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