As I am studying this SPI and DMA possibility, first I am a novice when it comes to this(DMA) and I am looking for some pointers from the experts.
Per the logic of DMA and the ability to off load many interrupts from the SPI transfer to the Peripheral DMA Controller (PDC). I see no examples of how this is to be done.
#1- Either it is so simple. I am missing it or it is the other end of the spectrum.
What would have to be done to AVR-DOS to have a DMA transfer performed on the SPI bus on the Xmegas?
Please don't take this the wrong way. Just looking at the benchmarks of the SPI transfer and the burdens being placed on the Xmega.
Since the device can handle many functions. With high speed xfers from the SPI, it will take its toll as pointed out here on the CPU. So as speed is great, in the real system, a more balanced approach might be more realistic as the target will be doing more than just SPI so a SD card.
Suggestions or am I moving/thinking in the wrong direction?
TIA,
Mark
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