@Per
Sorry, the osc register need no CCP, you are right at the point.
The clocking system is pretty complicated and has a lot of depencies. Maybe the PLL or DFLL also locks the bit. Or it is simple an errata (not all erratas are published...)
I would investigate, why the bit is turned ON after reset. This shouldn't happend.
@Mark
Indeed, a simple
[code:1:b2c93b5222]Cpu_ccp = 216 'Config Change Protection
Clk_ctrl = 1 'Use Int 32 MHz Osc
[/code:1:b2c93b5222]
could be done in basic, but a
[code:1:b2c93b5222]Cpu_ccp = 216 'Config Change Protection
Clk_ctrl.1 = 1 'Use Int 32 MHz Osc
[/code:1:b2c93b5222]
is compiled to the sequence
[code:1:b2c93b5222]ldi r23,&HD8
out CPU_CCP,r23
lds r23,CLK_CTRL
ori r23,&H01
sts CLK_CTRL,r23
[/code:1:b2c93b5222]
which give us 5 clock cycles for writing to CLK_CTRL after CCP. This will probaly fail.
Thats why I use assembler for those kind of timed register access.
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