Here is another example of manually setting up the Xmega clock, triggering the Change Protection Register, and watching for the clock source to be ready:
[code:1:a01d67f181]
Clockopt5:
'Set up the Xmega Clock.
'Run at 32 MHz from the Internal 32 MHz Osc, set by my code.
'Xmega runs on Int 2MHz Osc on Startup.
'This turns on the Int 32 MHz Osc, awaits it being ready, and switches to it.
'Don't forget the Configuration Change Register Protection Trigger before
'changing the uC's Clock Source.
'First turn ON the 32 MHz Int Osc:
'They wait until the Int 32 MHz Osc is ready to be used.
Osc_ctrl = 2 'Int 32 MHz Osc ON
Rvbit = 0 'Clear flag
While Rvbit = 0
'Read the Int 32 MHz Osc Status
Regdata = Osc_status 'Status of all Int Osc Sources
Rvbit = Regdata.1 'Int 32 MHz Osc Status, 1 = Ready
Wend
Cpu_ccp = 216 'Config Change Protection
Clk_ctrl = 1 'Use Int 32 MHz Osc
Return
[/code:1:a01d67f181]
JC
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